For the DRAM example chip that's been used throughout several of these posts (its because they are easy to decap and I have a lot of them), I started by manually pushing the chip around since I didn't have linear stages and taking pictures, trying to get 1/3 or so overlap on each side. However, these initial sets resulted in far inferior results compared to those made by using linear stages. That said, I need to make a comparison where I manually paste the images together. In any case, I first tried to use Hugin to manually stitch the images together. Unfortunately, while Hugin works very well for standard images, it seems to have issues with the vectorized patterns typical of ICs. I was only able to paste two well formed pictures together after setting 15 or so control points:
Thinking that I could do better, I looked into how to automate this process better. I cam across some information on the SIFT algorithm. Unfortunatly, while the SIFT algoirthm is patented by University of British Columbia, there are still some free implementations of it. The first I evaulated with autopano and later, after a reccomendation, was autostitch. Using the screwdriver pushed around die (as opposed to linear stage), with autopano, I go this:
However, I can't find a result using the linear stage version. I need ot rerun on that to confirm that autopano can't do better.Next I tried autostich. After some help from my friend on the linear stage set, I go this:
My friend that reccomended it to me is a bit better at using it though, and was able to get a much nicer image seen here (warning: 16MB). Scaled down local version:
His version is slightly more linear. My original image was quite distorted before he gave me the setting advice. In order to get good images with autostich, adjust quality settings to 100% (otherwise it will shrink it), set to linear, and adjust theta value low.
No comments:
Post a Comment