tag:blogger.com,1999:blog-534708807576459669.post6220023753424856468..comments2024-03-10T17:45:30.851-07:00Comments on IC reverse engineering and other adventures: SiDoku #1John McMasterhttp://www.blogger.com/profile/11714069658809228929noreply@blogger.comBlogger5125tag:blogger.com,1999:blog-534708807576459669.post-42537024415292474192012-03-05T00:01:49.516-08:002012-03-05T00:01:49.516-08:00That's the beauty of CMOS :-) But Q and Q# don...That's the beauty of CMOS :-) But Q and Q# don't change, if you think about it. It's only E vs. E#.Anonymoushttps://www.blogger.com/profile/12629131958615141514noreply@blogger.comtag:blogger.com,1999:blog-534708807576459669.post-33901363374635615312012-03-05T00:00:32.139-08:002012-03-05T00:00:32.139-08:00Yes, actually, I have. Can you send me an email at...Yes, actually, I have. Can you send me an email at vogelchr at vogel dot cx to discuss the details?Anonymoushttps://www.blogger.com/profile/12629131958615141514noreply@blogger.comtag:blogger.com,1999:blog-534708807576459669.post-24149151573940651192012-03-04T12:00:13.073-08:002012-03-04T12:00:13.073-08:00My official solution disagrees with yours as to Vd...My official solution disagrees with yours as to Vdd and Vss. Yours has ground on the right side but mine has it on the left. This of course results in Q and Q# changing place and the clock/enable line changing from active high to active low.<br /><br />My version is based purely on the active-area image in which the transistors on the right side are PMOS, which are presumably connected to the power rail. Did you make a mistake or did you see something we missed in our analysis?<br /><br />In any case you're pretty much correct. Here's my tracing, rotated into canonical orientation (Vdd rail at top): http://colossus.cs.rpi.edu/~azonenberg/downloads/cell07_traced.jpgAndrew Zonenberghttps://www.blogger.com/profile/16821509563933020441noreply@blogger.comtag:blogger.com,1999:blog-534708807576459669.post-83807430193114878282012-03-04T10:17:06.933-08:002012-03-04T10:17:06.933-08:00Wow, I didn't expect anyone to *read* this tha...Wow, I didn't expect anyone to *read* this that fast let alone solve it. I'll have to find something harder next time. Yes, that is correct. Originally when I was trying to decoded this I made the bad assumption that M2 wasn't part of the cell. Have a chip of interest? :)John McMasterhttps://www.blogger.com/profile/11714069658809228929noreply@blogger.comtag:blogger.com,1999:blog-534708807576459669.post-6447868538863554972012-03-04T05:12:45.752-08:002012-03-04T05:12:45.752-08:00Here's my guess:
It's a 1-bit latch with ...Here's my guess:<br /><br />It's a 1-bit latch with inverting and non-inverting outputs.<br /><br />I've made a drawing at http://vogel.cx/sidoku .Anonymoushttps://www.blogger.com/profile/12629131958615141514noreply@blogger.com